More recent electronic designs include three-dimensional integrated circuit designs (3DIC) or pseudo-three-dimensional (2.5D) integrated circuit designs where dies are arranged in an out-of-plane direction. These integrated circuit (IC) dies and shapes therein need to be properly aligned and arranged with respect to each other in order for the end product to function correctly or as intended. Even a single die design may include multiple metal layers, whereas conventional EDA tools present each metal layer of these multiple metal layers as an editable layer. Interconnecting these multiple layers or multiple dies has been severely cumbersome in that conventional approaches often load the layout of one layer (in a multi-layer, single die design) or one die (in a multi-die design) having the requisite interconnecting terminals or pins. These conventional approaches then identify the interconnects (e.g., bump pads interfacing with another die through a bump array, through-silicon vias interfacing another adjacent layer, etc.) on the layer or the die and implement the inter-die or inter-layer connectivity based on the design data provided by the layout of the layer or the die. Once the connectivity between these interconnects and the layer or die is completed. These conventional approaches then load another layout of another layer or die as well as the interconnects.
For example, in a three-dimensional (3D) integrated circuit (IC) design having a first die design stacking on top of a second die design, conventional approaches often load one die design (e.g., the first die) and the bump pads, which correspond to a bump array interfacing both the first and second die designs, to determine the connectivity between the two die designs via a bump array. More specifically, these conventional approaches load the layout of the first die and the bump pads and determine which bump pads will be assigned to what terminals or pins of the first die design. Once the connectivity is determined for the first die design, these conventional approaches then load the layout of the second die design and the bump pads, which also correspond to the same bump array, and attempt to connect the bump pads to the terminals or pins in the second die design.
Often, the connectivity implemented this way is improved or even optimized only between the bump array and the first layer or the die that is first loaded. On the other hand, the connectivity between the second layer or die design and the bump array is often much less improved and difficult to implement because the bumps in the bump array have already been assigned to certain terminals of the first layer or die design, and such assignment has been implemented without accounting for the information of the second layer or die design. As a result, conventional approaches may require numerous rounds of iterations to change the assignment of bumps in a bump array to corresponding terminals or pins so as to finally achieve a proper connectivity for the integrated circuit design.
Therefore, there exists a need for a method, system, and computer program product for implementing three-dimensional or multi-layer integrated circuit designs to address at least the aforementioned shortcomings and to implement integrated circuit designs in a much more efficient manner as far as at least time and computational resource utilizations are concerned.